The present invention relates to CMOS and specifically to CMOS circuits for use at the combination of higher temperatures and higher power supply voltages than have been available in the past.
Specific application needs for high temperature electronics include the need to operate at ambient temperatures in the 350.degree. C. range and the need to operate with higher than 5 volt power supply voltages. For example, some applications require operation with power supply voltages in the range of 12-14 volts or higher. Conventional CMOS circuits of the past, typically do not operate at temperatures above 180 to 200.degree. C. and then only operate with lower power supply voltages.
N-channel transistors subjected to a high drain to source voltage, Vds, generate a hole current in the body of the device near the p-well/n-ldd junction. This hole current is related to the maximum lateral electric field and flows through the p-well region to the nearest p-well contact. In a bulk technology this body hole current doesn't cause problems because the path to the nearest p-well contact is typically a low resistance vertical path due to it having a large cross-sectional area; whereas, in an SOI technology the presence of the buried oxide forces the current to flow laterally beneath the transistor out to a topside p-well contact through a highly resistive path. This path is highly resistive due to its small cross-sectional area.
This p-well connection is referred to as a body tie. Typical SOI designs allow for 10 to 20 microns of distance between the body tie and the conducting channel. The further the distance that the substrate current has to travel the higher the voltage drop is across the p-well. That is, as substrate current flows down the channel towards the body tie, i.e., Vss or ground, it creates a voltage drop. The voltage drop will eventually be enough to forward bias the N+ source to p-well diode thus causing a self-sustaining single transistor latch condition referred to as "snapback". This substrate current is normally known in the art as the cause of latch up.
Thus a need exists in specific applications for a CMOS device that will operate at temperatures in the 350.degree. C. range and with power supply voltages in the 12 to 14 volt range.